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ice40 ? hx - series ultra low - power fpga family october 03 , 2012 ( 1.32 ) data sheet ? 2007 - 2012 by lattice semico nductor corporation . all rights reserved. ( 1.32, 03 - oct - 2012 ) www.latticesemi.com 1 ? hx - series - optimized for high performance ? low cost package offerings ? 8 0% faster than ice65 ? proven, high - volume 40 nm, low - power cmos technology ? i ntegrated phase - locked loop (pll) ? clock multiplication/division for display , serdes , and memory interface applications ? up to 533 mhz pll output ? reprogrammable from a variety of methods and sources ? flexible programmable logic and programmable interconnect f abric ? 8 k look - up tables (lut4) and flip - flops ? low - power logic and interconnect ? complete ice cube ? development system ? windows ? and linux ? support ? vhdl and verilog logic synthesis ? place and route software ? design and ip core libraries ? low - cost iceman 40 hx de velopment board table 1 : ice40 hx ultra low - power programmable logic family summary part number hx 1k hx 4k hx 8k logic cells (lut + flip - flop) 1,28 0 3,520 7,68 0 ram4k memory blocks 16 20 32 ram4k ram bits 64 k 80k 128 k phase - l ocked loops (plls) 1 2 2 configuration bits (maximum) 245 kb 533 kb 1,057 kb core operating power 0 khz 1 267 a 667 a 1100 a maximum programmable i/o pins 96 107 206 maximum differential input pairs 12 14 26 package code area m m pitch mm pi o: max i/ o (lvds) 225 - ball uc bga cm225 7x7 0.4 178(23) 132 - ball cs bga cb132 8x8 0.5 95(11) 95(12) 95(12) 256 - ball ca bga ct256 14x14 0.8 206(26) 100 - pin vqfp 2 vq100 14x14 0.5 72(9) 144 - pin tqfp t q144 20x20 0.5 96(12 ) 107(14 ) note 1: at 1.2v vcc, 25c 2 : no pll available figure 1 : ice40 hx - series family architectural features i / o b a n k 0 i / o b a n k 2 i / o b a n k 1 i / o b a n k 3 p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p l b p r o g r a m m a b l e i n t e r c o n n e c t p r o g r a m m a b l e i n t e r c o n n e c t 2 6 7 a a t f = 0 k h z ( t y p i c a l ) n v c m p l b p l b p l b 4 k b i t r a m 4 k b i t r a m p l b p l b p l b p l b n o n v o l a t i l e c o n f i g u r a t i o n m e m o r y ( n v c m ) p l b p l b p l b p l b f o u r - i n p u t l o o k - u p t a b l e ( l u t 4 ) c a r r y l o g i c f l i p - f l o p w i t h e n a b l e a n d r e s e t c o n t r o l s p r o g r a m m a b l e l o g i c b l o c k ( p l b ) 8 l o g i c c e l l s = p r o g r a m m a b l e l o g i c b l o c k p l b p l b p l b p l b p r o g r a m m a b l e i n t e r c o n n e c t p l b p l b s p i c o n f i g p l l p h a s e - l o c k e d l o o p
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 2 ordering information figure 2 describes the ice40 hx ordering codes for all packaged components. see the separate dieplus data sheets when ordering die - based products. see the separate ice4 0 pinout excel files for package and pinout specifications. figure 2 : ice40 hx ordering codes (packaged, non - die components) part number luts supply voltage temp. ice40hx1k - vq100 1,280 1.2v ind ice4 0hx1k - tq144 1,280 1.2v ind ice40hx1k - cb132 1,280 1.2v ind ice40hx4k - cb132 3,520 1.2v ind ice40hx4k - tq144 3,520 1.2v ind ice40hx8k - cb132 7,680 1.2v ind ice40hx8k - cm225 7,680 1.2v ind ice40hx8k - ct256 7,680 1.2v ind ice40 hx 8k - cm225 225 - ball chip - scale bga package (7x7 mm footprint, 0.4 mm pitch) h i g h p e r f o r m a n c e s e r i e s l o g i c c e l l s p a c k a g e s t y l e i c e 4 0 h x 8 k - c m 2 2 5 p a c k a g e l e a d s c m = u c b g a ( 0 . 4 m m p i t c h ) c b = c s b g a ( 0 . 5 m m p i t c h ) c t = c a b g a ( 0 . 8 m m p i t c h ) v q = v e r y t h i n q u a d f l a t p a c k ( 0 . 5 m m p i t c h ) t q = t h i n q u a d f l a t p a c k ( 0 . 5 m m p i t c h ) 1 k , 4 k , 8 k
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 3 electrical characteristics all parameter limits are specified under worst - case supply voltage, junction temperature, and processing conditions . absolute maximum ratings stresses beyond those listed under table 2 may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions is n ot implied. exposure to absolute maximum conditions for extended periods of time adversely affects device reliability. table 2 : absolute maximum ratings symbol description minimum maximum units vcc core supply voltage C 0.5 1.42 v vpp_2v5 vpp_2v5 nvcm programming and operating supply v vpp_fast optional fast nvcm programming supply v vccio_0 vccio_1 vccio_2 vccio_3 spi_vcc i/o bank supply voltage (i/o banks 0, 1, 2 and 3 plus spi interface) C 0.5 4.00 v vin_0 vin_1 vin_2 vin_ spi vin_3 voltage applied to pio pin within a specific i/o bank (i/o banks 0, 1, 2 and 3 plus spi interface) C 1.0 3.6 v vccpll analog voltage supply to the phase locked loop (pll) C 0.5 1.3 0 v i out dc output current per pin 20 ma t j junction temperatur e C 55 125 c t stg storage temperature, no bias C 65 150 c recommended operating conditions table 3 : recommended operating conditions symbol description minimum nominal maximum units vcc core supply voltage high performance, low - power 1.14 1.20 1.26 v vpp_2v5 1 vpp_2v5 nvcm programming and operating supply release from power - on reset 1.30 3.47 v configure from nvcm 2.30 3.47 v nvcm programming 2.30 3.00 v vpp_fast 2 optional fast nvcm programming supply leave unconnec ted in application spi_vcc spi interface supply voltage 1.71 3.47 v vccio_0 vccio_1 vccio_2 vccio_3 spi_vcc i/o standards, all banks lvcmos33 2.70 3.30 3.47 v lvcmos25, lvds 2.38 2.50 2.63 v lvcmos18, sublvds 1.71 1.80 1.89 v lvcmos15 1.43 1.5 0 1.58 v vccpll 3 analog voltage supply to the phase locked loop (pll) 1.14 1.2 0 1.26 v t a ambient temperature C 40 85 c t prog nvcm programming temperature 10 25 30 c notes : 1. vpp_2v5 must be connected to a valid voltage, when the ice40hx device is act ive. 2. vpp_fast, used only for fast production programming, must be left floating or unconnected in application. 3. vccpll must be tied to vcc when pll is not used.
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 4 i/o characteristics table 4 : pio pin electrical characteristics symbol description conditions minimum nominal maximum units i l input pin leakage current v i n = vccio max to 0 v 10 a i oz three - state i/o pin (hi - z) leakage current v o = vccio max to 0 v 10 a c pio pio pin input capacitance 6 pf c gbin gbin globa l buffer pin input capacitance 6 pf r pullup internal pio pull - up resistance during configuration vccio = 3.3v 6 0 k vccio = 2.5v 8 0 k vccio = 1.8v 12 0 k vccio = 1.5v 160 k v hyst input hysteresis vccio = 1.5 v to 3.3v 50 mv note: all characteristics are characterized and may or may not be tested on each pin on each device. single - ended i/o characteristics table 5 : i/o characteristics i/o standard nominal i/o bank supply voltage input voltage (v) output voltage (v) output current at voltage (ma) v il v ih v ol v oh i ol i oh lvcmos33 3.3v 0.80 2.0 0 0.4 2.4 0 8 8 lvcmos25 2.5v 0. 70 1. 7 0 0.4 2.00 6 6 lvcmos18 1.8v 35% vccio 65% vccio 0.4 1.40 4 4 lvcmos15 1.5 v 35% vccio 65% vccio 0.4 1.20 2 2
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 5 differen tial inputs figure 3 : differential input specifications input common mode voltage : differential input voltage : | | table 6 : recommended operating conditions for differential inputs i/o standard vccio_3 (v) v id (mv) v icm (v) min nom max min nom max min nom max lvds 2.38 2.50 2.63 250 350 450 sublvds 1.71 1.80 1.89 100 150 200 differential outputs figure 4 : differential output specifications out put common mode voltage : differential out put voltage : | | table 7 : recommended operating conditions for differential outputs i/o standard vccio_x (v) v od (mv) v ocm (v) min nom max r s r p min nom max min nom max lvds 2.38 2.50 2.63 150 140 300 350 400 sublvds 1.71 1.80 1.89 270 120 100 150 200 v c c i o _ 3 d p x x b d p x x a i c 4 0 d i f f e r e n t i a l i n p u t 1 0 0 g n d v i d v i c m 5 0 % v i n _ b v i n _ a i n p u t c o m m o n m o d e v o l t a g e d i f f e r e n t i a l i n p u t v o l t a g e 1 % i c 4 0 d i f f e r e n t i a l o u t p u t p a i r r p r s r s g n d v o d v o c m 5 0 % v o u t _ b v o u t _ a o u t p u t c o m m o n m o d e v o l t a g e d i f f e r e n t i a l o u t p u t v o l t a g e v c c i o _ x 1 %
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 6 ac timing guidelines the following examples provide some guidelines of device performance. the actual performance depends on the sp ecific application and how it is phys ically implemented in the ice40 fpga using the lattice icecube2 software. the following guidelines assume typical conditions (vcc = 1.0 v or 1.2 v as specified, temperature = 25 ?c). apply derating factors using the i cecube2 timing analyzer to adjust to other operating regimes. programmable logic block (plb) timing table 8 provides timing information for the logic in a programmable logic block (plb), which includes the paths sh own in figure 5 and figure 6 . figure 5 plb sequential timing circuit figure 6 plb combinat ional timing circuit table 8 : typical programmable logic block (plb) timing nominal vcc 1.2 v units description typ. sequential logic paths f toggle gbin input gbin input flip - flop toggle freq uency. dff flip - flop output fed back to lut4 input with 4 - input xor, clocked on same clock edge 256 mhz t cko dff clock input pio output logic cell flip - flop (dff) clock - to - output time, measured from the dff clk input to pio output, including interconnect delay. 3.9 ns t gbcklc gbin input dff clock input global buffer input (gbin) delay, though global buffer (gbuf) clock network to clock input on the logic cell dff flip - flop. 1. 5 ns t suli pio input gbin input minimum setup time on pio input, through lut4, to dff flip - flop d - input before active clock edge on the gbin input, including interconnect delay. . 67 ns t hdli gbin input pio input minimum hold time on pio input, through lut4, to dff flip - flop d - input after active clock edge on the gbin input, includi ng interconnect delay. 0 ns combinational logic paths t lut4in pio input lut4 input asynchronous delay from pio input pad to adjacent plb interconnect. 1.8 ns t ilo lut4 input lut4 output logic cell lut4 combinational logic propagation delay, regardless o f logic complexity from input to output. 0.34 ns t lut4in lut4 output pio output asynchronous delay from adjacent plb interconnect to pio output pad. 3.7 ns l o g i c c e l l p a d p i o p a d p i o g b i n g b u f l u t 4 d q d f f l o g i c c e l l l u t 4 p a d p i o p a d p i o l o g i c c e l l
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 7 programmable input/output (pio) block table 9 provides t iming information for the logic in a programmable logic block (plb), which includes the paths shown in figure 7 and figure 8 . the timing shown is for the lvcmos25 i/o stan dard in all i/o banks. the icecube2 development software reports timing adjustments for other i/o standards. figure 7 : programmable i/o (pio) pad - to - pad timing circuit figure 8 : programmable i/o (pio) sequential timing circuit table 9 : typical programmable input/output (pio) timing (lvcmos25) nominal vcc 1.2 v units description typ. synchronous output paths t o cko outff clock input pio output delay from clock input on outff output flip - flop to pio output pad. 3.1 ns t gbckio gbin input outff clock input global buffer input (gbin) delay, though global buffer (gbuf) clock network to clock input on the pio outff ou tput flip - flop. 1.4 ns synchronous input paths t supdin pio input gbin input setup time on pio input pin to inff input flip - flop before active clock edge on gbin input, including interconnect delay. 0 ns t hdpdin gbin input pio input hold time on pio inpu t to inff input flip - flop after active clock edge on the gbin input, including interconnect delay. 1.6 ns pad to pad t padin pio input inter - connect asynchronous delay from pio input pad to adjacent interconnect. 1.8 ns t pado inter - connect pio output asy nchronous delay from adjacent interconnect to pio output pad including interconnect delay. 3.4 ns p a d p i o p a d p i o p a d p i o g b i n g b u f p a d p i o d q i n f f d q o u t f f
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 8 ram4k block table 10 provides timing information for the logic in a ram4k block, which includes the paths shown in figure 9 . figure 9 : ram4k timing circuit table 10 : typical ram4k block timing nominal vcc 1.2 v description typ. write se tup /hold time t suwd pio input gbin input minimum w rite data setup time on pio inputs before active clock edge on gbin input, include interconnect delay. 0.44 ns t hdwd gbin input pio input minimum w rite data hold time on pio inputs after active clock edge on gbin input, including interconnect delay. 0 ns read clock - output - time t ckord rclk clock input pio output clock - to - output delay from rclk input pin, through ram4k rdata output flip - flop to pio output pad, including interconnect delay. 4.1 ns t gbckrm gbin input rclk clock input global buffer input (gbin) delay, though global buffer (gbuf) clock network to the rclk clock input . 1.4 ns write and read clock characteristics t rmwckh wclk rclk wclk rclk write clock high time 0.30 ns t rmwckl write clock low time 0.35 ns t rmwcyc write clock cycle time 0.71 ns f wmax sustained write clock frequency 256 mhz p a d p i o p a d p i o g b i n g b u f w d a t a w c l k r d a t a r c l k r a m 4 k r a m b l o c k ( 2 5 6 x 1 6 ) g b i n g b u f
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 9 phase - locked loop (pll) block table 11 provides timing information for the phase - locked loop (pll) blo ck shown in figure 10 . figure 10 : phase - locked loop (pll) table 11 : phase - locked loop (pll) block timing symbol from to nominal vcc 1. 2 v units description min. typical max. frequency range f ref input clock frequency range 10 133 mhz f out output clock frequency range (cannot exceed maximum frequency supported by global buffers) 16 533 mhz duty cycle pll ij input duty c ycle 35 65 % tw hi input clock high time 2.5 ns tw low input clock low time 2.5 ns pll o j output duty cycle 45 55 % fine delay t fd tap fine delay adjustment, per tap 165 p s pll taps fine delay adjustment settings 0 15 taps pll fd am maximum delay adjustment 2.5 ns jitter pll ipj input clock period jitter +/ - 300 ps pll opj pllout output period jitter 1% or 100 +/ - 1.1% output period or 110 ps lock/reset time t lock pll lock time after receive stable, monotoni c referenceclk input 50 s tw rst minimum reset pulse width 20 ns notes: 1. output jitter performance is affected by input jitter. a clean reference clock < 100ps jitter must be used to ensure best jitter performance. 2. the output jitter specificati on refers to the intrinsic jitter of the pll. r e f e r e n c e c l k r e s e t b y p a s s p l l o u t e x t f e e d b a c k l o c k d y n a m i c d e l a y [ 3 : 0 ] l a t c h i n p u t v a l u e p l l
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 10 internal configuration oscillator frequency table 12 shows the operating frequency for the ice40s internal configuration oscillator. table 12 : internal oscillator frequency at vcc = 1.2v symbol oscillator mode frequency (mhz) description min. max. f oscd default 7 10 default oscillator frequency. slow enough to safely operate with any spi serial prom. f oscl low frequency 21 30 supported by most spi serial flash proms f osch high frequency 35 50 supported by some high - speed spi serial flash proms off 0 0 oscillator turned off by default after configuration to save power. configuration timing table 13 shows the maximum time to configure an ice40 hx device, by oscillator mode. the calculations use the slowest frequency for a given oscillator mode from table 12 and the maximum configuration bitstream size f rom table 1 , which includes full ram4k block initialization. the configuration bitstream selects the desired oscillator mode based on the performance of the configuration data source. table 13 : typical spi master or nvcm configuration timing by oscillator mode symbol description device default low freq. high freq. units t config l time from when minimum power - on reset (por) threshold is reached until user application starts. ice40 hx 1k 53 25 11 ms ice40 hx 4k 230 110 50 ms ice40 hx 8k 230 110 50 ms table 14 provides timing for the creset_b and cdone pins. table 14 : general configuration timing symbol from to description all grades units min. max. t creset_b crest_b crest_b minimum creset_b low pulse width required to restart configuration, from falling edge to rising edge 200 ns t done_io cdone high pio pins active number of configuration clock cycles after cdone goe s high before the pio pins are activated. 49 clock cycles spi peripheral mode (clock = spi_sck, cycles measured rising - edge to rising - edge) depends on spi_sck frequency table 15 provides various timing spe cifications for the spi peripheral mode interface. table 15 : spi peripheral mode timing symbol from to description all grades units min. max. t cr_sck cres e t_b spi_sck minimum time from a rising edge on creset_b until the fir st spi write operation, first spi_sck. during this time, the ice40 hx fpga is clearing its internal configuration memory 300 s t suspisi spi_si spi_sck setup time on spi_si before the rising spi_sck clock edge 12 ns t hdspisi spi_sck spi_si hold time on spi_si after the rising spi_sck clock edge 12 ns t spisckh spi_sck spi_sck spi_sck clock high time 20 n s t spisckl spi_sck spi_sck spi_sck clock low time 20 n s t spisckcyc spi_sck spi_sck spi_sck clock period* 40 1,000 n s f spi_sck spi_sck spi_sck sustained spi_sck clock frequency* 1 25 mhz * = applies after sending the synchronization pattern.
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 11 power consumption characteristics core power table 16 shows the power consumed on the internal vcc supply rail w hen the device is filled with 16 - bit binary counters, measured with a 32.768 khz and at 32.0 mhz table 16 : vcc power consumption for device filled with 16 - bit binary counters symbol description vcc ice40hx1k ice40hx4 k ice40 hx 8k un its typical 1 typical 1 typical 1 i cc0 k f =0 1.2v 267 667 1100 a i cc32k f .768 khz 1.2v 297 741 1222 a i cc32m f = 32.0 mhz 1.2v 4 12 13 ma note 1: at 25c i/o power table 17 provides the static cur rent by i/o bank. the typical current for i/o banks 0, 1, 2 and the spi bank is not measurable within the accuracy of the test environment. the pios in i/o bank 3 use different circuitry and dissipate a small amount of static current. table 17 : i/o bank static current (f = 0 mhz) symbol description typical maximum units i cco_0 i/o bank 0 static current consumption per i/o bank. f = 0 mhz. no pio pull - up resistors enabled. all inputs grounded. all outputs driving low. ? 1 ua i cco_1 i/o bank 1 ? 1 ua i cco_2 i/o bank 2 ? 1 ua i cco_3 i/o bank 3 ? 1 ua i cco_spi spi bank ? 1 ua note: the typical static current for i/o banks 0, 1, 2, and the spi bank is less than the accuracy of the device tester. power estimator to estimate the power consumption for a specific application, please download and use the ice40 hx power estimator spreadsheet our use the power estimator built into the icecube2 software.
ice40 hx - series ultra - low power family lattice se miconductor corpo ration ( 1.32, 03 - oct - 2012 ) www.latticesemi.com/ 12 revision hi st ory version date description 1.32 03 - oct - 2012 updated table 1 to remove ice40hx640, add tq144 package , note 1 to include 25c, and unified package nomenclature. updated figure 2 ordering codes to include all part numbers. added note 1: at 25c to table 16 vcc power. 1.31 30 - mar - 2012 updated table 1 1.3 22 - mar - 2012 production release updated notes on table 3 : recommended operating conditions updated values in table 4 , table 5 table 12 , table 13 and table 17 1.21 5 - mar - 2012 updated figure 3 and figure 4 to specify ice40 1.2 13 - feb - 2012 updated company name 1.1 15 - d ec - 2011 moved package specifications to ice40 pinout excel files. updated table 1 maximum ios. 1.01 31 - oct - 2011 added 640, 1k and 4k to table 13 configuration times . upd ated table 1 maximum ios. 1.0 11 - jul - 2011 initial release ? 2012 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.lattices emi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. lattice semiconductor corporation 5555 n.e. moore cour t hillsboro, oregon 97124 - 6421 united states of america tel: +1 503 268 8000 fax: +1 503 268 8347 cumentati on s ervi ces by prevail ing technol ogy, inc. ( www.pre vai ling - technol ogy.com )

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